Modern digital integrated circuits such as central processing units (CPUs) are typically capable of operating with several different clock frequencies. Assume that a CPU can reduce its clock frequency while still meeting the processing requirements of an application that is running on the CPU. As is well known, a reduction in the clock frequency of the CPU proportionally reduces the CPU power consumption. With a lower clock frequency less power is consumed because there are fewer signal level changes within a given time period.
As is also well known, the power consumption of a digital circuit is quadratically proportional to the operating voltage. Therefore, decreasing the voltage level of the operating voltage (i.e., the supply voltage) and reducing the clock frequency can provide significant power savings in a digital circuit.
Dynamic Voltage Scaling (DVS) is a power management technique in which pre-determined voltage values (within a voltage table) are used for each requested operating clock frequency of a CPU. The voltage levels that are defined in the voltage table must be carefully selected in order to adequately cover all process and temperature corners so that the CPU will function correctly at each clock frequency.
Adaptive Voltage Scaling (AVS) is a power management technique in which the supply voltage of a digital integrated circuit is adjusted automatically. The supply voltage is adjusted using closed loop feedback to a minimum level that is required for the proper operation of the integrated circuit at a given clock frequency.
The major difference between Dynamic Voltage Scaling (DVS) and Adaptive Voltage Scaling (AVS) is that the Adaptive Voltage Scaling (AVS) automatically measures variation of the process and temperature in order to balance the supply voltage and system delay (digital cell delay) that is due to closed loop feedback. This means that the supply voltage in the AVS system is automatically reduced at lower temperatures and for faster silicon. As the supply voltage is reduced, the power consumption is also reduced.
FIG. 1 illustrates a block diagram of an embodiment of an exemplary prior art Adaptive Voltage Scaling (AVS) system 100. AVS system 100 comprises a System-on-a-Chip (SoC) unit 110 and an Energy Management Unit (EMU) 120. The System-on-a-Chip (SoC) unit 110 comprises a Clock Management Unit (CMU) 130, a Variable Voltage Domain CPU System 140, a Hardware Performance Monitor (HPM) 150, and an Advanced Power Controller (APC) 160. The Hardware Performance Monitor (HPM) 150 is located within the Variable Voltage Domain CPU System 140.
The Clock Management Unit (CMU) 130 receives a system clock signal from a system clock unit (not shown in FIG. 1). The Clock Management Unit (CMU) 130 provides clock frequencies for the central processing unit (CPU) (also not shown in FIG. 1). The Clock Management Unit (CMU) 130 also provides clock frequencies for the Hardware Performance Monitor (HPM) 150. The clock frequencies that are provided to the Hardware Performance Monitor (HPM) 150 are represented by the designation HPM CLOCK.
The Hardware Performance Monitor (HPM) 150 tracks gate delays in the current operational conditions. The CPU system and the Hardware Performance Monitor (HPM) 150 are in the Variable Voltage Domain CPU System 140. The Hardware Performance Monitor (HPM) 150 outputs a performance code to the Advanced Power Controller (APC) 160. The performance code indicates the propagation delay of digital gate cells. The Advanced Power Controller (APC) 160 processes the delay data and requests appropriate changes to the supply voltage.
The Advanced Power Controller (APC) 160 is coupled to and communicates with the Energy Management Unit (EMU) 120. In one embodiment the coupling between the Advanced Power Controller (APC) 160 and the Energy Management Unit (EMU) 120 is a PowerWise® interface (PWI). The mark PowerWise® is a registered trademark of the National Semiconductor Corporation. The Advanced Power Controller (APC) 160 sends a request to the Energy Management Unit (EMU) 120 to change the supply voltage. The Energy Management Unit (EMU) 120 provides the requested supply voltage level to the System-on-a-Chip (SoC) 110. The adjustable supply voltage from the Energy Management Unit (EMU) 120 is designated VAVS in FIG. 1.
The operating system of a modern central processing unit (CPU) may support a real time scheduling of performance levels. Each performance level may have associated with it a specific value of operating clock frequency. The operating system is capable of selecting an operating clock frequency for which the CPU performance is minimized on a real time basis and for which the deadlines of a particular application are still met. For example, while an MPEG4 movie encoding application is running, a performance scheduling algorithm of the operating system may predict and change the performance level of the CPU in ten millisecond (10 ms) intervals.
The Hardware Performance Monitor (HPM) 150 tracks gate delays in the current operational conditions. The Hardware Performance Monitor (HPM) 150 outputs a performance code to the Advanced Power Controller 160. The performance code indicates the propagation delay of digital gate cells. In particular, Hardware Performance Monitor (HPM) 150 sends the performance code to the Advanced Power Controller 160. The Advanced Power Controller 160 then subtracts the performance code from a standard Reference Calibration Code (RCC) to obtain an error signal.
The error signal is referred to as “Slack Time”. The Slack Time error signal comprises a digital error signal in a two's complement number format. If the Slack Time is positive an increase in voltage is required. If the Slack Time is negative a decrease in voltage is required. The Slack Time error signal is provided to a Compensation Unit (not shown) within the Advanced Power Controller 160. Based on the value of the Slack Time error signal, the Compensation Unit sends a signal to the Energy Management Unit (EMU) 120 to cause the Energy Management Unit (EMU) 120 to adjust the value of the adjustable output voltage (VAVS) of Energy Management Unit (EMU) 120.
Modern System-on-a-Chip (SoC) digital logic circuits may consume large amounts of power both in terms of leakage power and dynamic power. Leakage power is the power that is consumed when no switching activity occurs within the logic circuitry. Dynamic power is the power that is consumed by the logic circuitry to alter its internal states (e.g., charging and discharging internal nodes).
When a closed loop adaptive voltage scaling system of the type illustrated in FIG. 1 minimizes the supply voltage, both the dynamic power and the leakage power are minimized. The expression for the power of the System-on-a-Chip (Soc) is given by the expression:P=αCV2fCLK+VIL  Eq. (1)
P is the total power of the System-on-a-Chip (SoC). Alpha (α) is a switching activity factor. Alpha (α) represents the percentage of nodes that are switching at each clock cycle. C is the node capacitance inside the SoC. The expression fCLK is the SoC clock frequency. V is the supply voltage. The expression IL is the leakage current. Equation (1) assumes rail-to-rail switching for the CMOS logic.
In modern implementations of System-on-a-Chip (SoC) systems there are multiple independent functional blocks. These blocks may include general purpose processor cores, digital signal processing (DSP), and hardware accelerators for specific functions like Digital Video Broadcasting-Handheld (DVB-H) reception, encoding and decoding in MPEG 2/MPEG 4/VC1 video standards, baseband processing and the like. The multiple independent functional hardware blocks are used for different functions because it is much more efficient in terms of power consumption to use a hardware implementation rather than a software implementation. For example, DVB-H decoding that is performed in a dedicated hardware block is more efficient in terms of power consumption than DVB-H decoding that is performed using software running in a central processing unit (CPU).
In addition, the individual multiple independent functional hardware blocks are activated only when they are needed. When they are not required, the individual multiple independent functional hardware blocks remain inactive to reduce power consumption.
There are several independent functional hardware blocks inside a System-on-a-Chip (SoC) system. Each hardware block has its own characteristic usage requirements and operating frequencies (which may also be variable frequencies). Each of the hardware blocks can further reduce its power consumption by using techniques like Dynamic Voltage Scaling (DVS) and Adaptive Voltage Scaling (AVS). This requires that an Adaptive Voltage Scaling (AVS) system 100 of the type that is shown in FIG. 1 be implemented in parallel for each independent functional hardware blocks inside the System-on-a-Chip (SoC) system. This type of arrangement provides an optimal supply voltage for each of the independent functional hardware blocks.
However, there are two main disadvantages with this approach. First, the number of required adjustable voltage regulators (and associated external components) may be too large. That is, the number of circuit elements that are required to implement this solution may be too large for this solution to be feasible in a size-constrained portable device. Second, even if the size and complexity problems could be overcome, the cost of all of the required hardware may be too great for a particular application.
Therefore, there is a need in the art for a system and method that allows a system architect to define an optimum balance between power efficiency and the number of independent voltage domains (and associated adjustable voltage regulators and their external components) in terms of size and cost while optimizing the power consumption of a complex, multi-function System-on-a-Chip (SoC) system. There is a need in the art for a system and method that is capable of efficiently providing accurate adaptive voltage scaling (AVS) for a System-on-a-Chip (SoC) system that operates with a plurality of clock domains inside a single voltage domain.